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IEEE Defect and Data-Driven Testing
(D3T 2008)

October 30-31, 2008
Santa Clara, CA

Held in Conjunction with ITC Test Week (ITC 2008)

http://d3t.tttc-events.org/

CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Technology scaling is introducing yield as main issue to design and test engineers. Various types of defects are presenting unique challenges to the yield enhancement community. New test data based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-50nm technology nodes and their impact on yield. Data-driven testing (DDT) has been in practice for a number of years and often used for yield learning and analysis. It is now gaining attention more than ever in adaptive test. DDT uses data to reduce defect levels, increase reliability, and to diagnose and solve yield problems. DDT can provide feedbacks on which tests to add/remove, or test subsets (e.g. reduced MINVDD test sets). It can also be utilized for improving quality of logic test patterns (e.g. small delay defect, defect-based) vs. outlier analysis tests (e.g. MINVDD, IDDQ). However, test data has not been easily accessible by smaller companies and researchers in academia. These issues will be discussed in this year’s D3T workshop.

Submissions

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To present at the workshop, submit a postscript or Acrobat (PDF) version of an extended abstract of at least 1000 words via e-mail to the Program Chair by Aug. 26, 2008. Each submission should include full name and address of each author, affiliation, telephone number, fax and e-mail address. The presenter should also be identified. Camera-ready papers for inclusion in the digest of papers will be due on Sept. 26, 2008. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Proposals for embedded tutorials, debates, panel discussions or “spot-light” presentations describing industrial experiences are also invited.

Key Dates

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Submission deadline: August 26, 2008
Notification of acceptance: September 19, 2008
Final copy deadline: September 26, 2008

Additional Information
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Technical Program Submissions:
Mohammad Tehranipoor
University of Connecticut

E-mail: tehrani@engr.uconn.edu

Committees
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Organizing Committee

General Chair
Rob Aitken, ARM

Program Chair
Mohammad Tehranipoor, Univ. of Connecticut

Vice Program Chair
Al Crouch, Asset-Intertech

Finance Chair
Sankaran M. Menon, Intel

Publicity Chair
Arani Sinha, AMD

Program Committee

Tom Bartenstein, Cadence
Ken Butler, TI
Krish Chakrabarty, Duke Univ.
Sreejit Chakravarty, LSI Logic
John Carulli, TI
Robert Daasch, Portland State Univ.
Jennifer Dworak, Brown University
Patrick Girard, LIRRM
Rohit Kapur, Synopsys
Ajay Koche, Verigy
Mike Laisne, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Teresa McLaurin, ARM
Martin Margala, U-Mass
Amit Nahar, TI

Steering Committee

Sankaran Menon, Intel
Adit Singh, Auburn Univ.
Hank Walker, Texas A&M
Hans Manhaeve, Q-Start Test
Jim Plusquellic, U. New Mexico

For more information, visit us on the web at: http://d3t.tttc-events.org/

The Defect and Data-Driven Testing (D3T 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Doug J. YOUNG
SV Probe Inc.
- USA
Tel.
E-mail dyoung@svprobe.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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